South Korea's DEEPX Completes Tape-Out of Samsung 2nm Chip: 100B-Parameter Inference at 5W, a Watt-Level Turning Point for Edge AI?

On November 10, 2026, South Korean fabless AI chip company DEEPX announced that its second-generation AI inference chip, DX-M2, had completed tape-out on Samsung Electronics Foundry's 2nm GAA process. The design target is to run large language models and vision-language models at roughly 5W of power. According to The Korea Times, the chip was also named a CES 2027 AI Innovation Award honoree the same day, marking DEEPX's third consecutive year of winning at CES. According to the timeline disclosed by the company, the first silicon will arrive from the fab in March 2027, customer evaluation sampling will begin in Q2, initial mass production will start in Q4, and full global mass production will begin in 2028.

Completion of tape-out means the chip design data has been formally handed over to the foundry, and the hardware-level design work has come to an end. DEEPX has set mass production for 2028; DX-M2 is currently a candidate solution whose design is finalized but whose performance remains to be verified.

Between Two Generations: Where Does the Leap from 4B to 100B Come From?

DX-M1 is based on Samsung's 5nm process, supports models with up to 4B parameters, is equipped with up to 8GB of LPDDR4x/5 memory, and keeps power consumption below 5W. Since entering mass production in August 2025, as of October 2026 it has accumulated 88 commercial purchase orders in more than 10 countries worldwide, with a contract value of about $13.3 million, covering eight industries. Customers include Hyundai Motor Group's robotics lab.

DX-M2's design target is to raise the runnable model scale from 4B parameters to 100B parameters with almost unchanged power consumption, while increasing memory configuration to 96GB of LPDDR5X. This leap depends on deep architecture-level customization for the sparse activation characteristics of mixture-of-experts models. The key to the MoE architecture is that even if the total number of parameters is enormous, only a small subset of expert modules is activated during each inference, so actual computation and power consumption are far lower than those of an equivalent dense model.

DX-M1 once demonstrated a detail in an international media demo: butter was placed on the chip, and the butter did not melt. According to U.S. IT media Tom's Hardware, this dairy-based benchmark genuinely reflects the chip's extremely low heat dissipation. If DX-M2 can extend the same thermal management capability to the hundred-billion-parameter scale, it will mean a qualitative change in the density of AI capabilities in industrial robots and smart factory terminals.

Who Faces the Direct Impact—and Who Is Waiting for the Opportunity

For robot and industrial terminal manufacturers, DX-M2 offers a technical option that did not previously exist. If DX-M2's 5W/100B specifications hold up in testing, it will open a path to running general large models locally, without the cloud and with simple thermal design. DEEPX's existing customer base is the first group of potential upgrade users.

For Samsung Foundry, DX-M2 is an important commercial validation milestone for its 2nm GAA process. DEEPX chose Samsung SF2P for tape-out, providing Samsung's 2nm process with a real-world scenario for energy-efficient AI inference.

For NVIDIA, the direct threat is limited in the short term, but the long-term structural pressure is worth watching. DX-M2 targets ultra-low-power industrial terminals at the 5W level. Once on-device large-model inference matures, some compute demand that originally had to go to the cloud will be absorbed at the device end, creating an indirect diversion of NVIDIA's cloud inference business.

For developers, practical usability depends on when DEEPX opens its software ecosystem. Whether DX-M2 can continue DX-M1's approach of supporting standard AI framework integration and cover mainstream open-source large models will be preliminarily verified during the Q2 2027 sampling stage.

Side-by-Side: Qualcomm's Timeline and DEEPX's Positioning Divergence

Qualcomm CEO Cristiano Amon once said that AI companies are demanding that smartphones run 100B-parameter models continuously by 2028. Qualcomm's target date for 100B parameters on consumer mobile platforms is 2028, while DEEPX's customer sampling for DX-M2, aimed at industrial terminals, is already scheduled for Q2 2027.

The constraints on phone chips are battery life, heat, and thin bodies, while they also need to support multitasking across operating systems, graphics, and communications. The constraints on industrial NPUs are thermal stability under long periods of full-load inference, modular power delivery, and throughput optimization for specific vertical tasks. DEEPX positions DX-M2 as an industrial-purpose chip that can run generative AI without a cloud connection, giving up the breadth of the consumer ecosystem in exchange for deep targeting of industrial scenarios.

Judging from DEEPX's own commercial progress, DX-M1's data provides a pragmatic reference point: 88 purchase orders and $13.3 million in contract value, averaging about $150,000 per order. The average is relatively small, indicating that customers are currently mainly conducting small- and medium-batch validation. DEEPX raised its 2026 revenue target to about KRW 60 billion, roughly 18 times its actual revenue of KRW 330 million in 2025.

Two Decisive Signals, and Where the Risks Lie

The central question around DX-M2 is not the tape-out itself. There are two real validation milestones: first, functionality and yield testing after the first silicon arrives in March 2027, when it will be possible to preliminarily confirm whether the design targets hold at the physical level; second, actual scenario testing after customer sampling in Q2 2027, when feedback from industrial customers will determine whether DX-M2 can replicate DX-M1's path to opening up the market.

The main risks come from two directions. The first is process risk: the maturity and yield of Samsung's 2nm GAA process are still in an early ramp-up stage. The previous-generation DX-M1 achieved a high yield of 91.1% on Samsung 5nm, but the complexity of the 2nm node is far higher than that of 5nm, and yield performance is difficult to extrapolate linearly. The second is the last mile of the application ecosystem: even if silicon performance meets the target, industrial terminal manufacturers typically need 12 to 18 months for system design and certification from intent to purchase to large-scale deployment. This means that even if DX-M2's specifications are perfect, large-scale market impact will not appear before 2029.

If, after customer sampling in Q2 2027, an industrial system manufacturer publicly announces a product development plan based on DX-M2, it will show that the 5W/100B design target has passed preliminary silicon validation and that edge large-model inference has truly entered a plannable product roadmap. Conversely, if the sampling stage is delayed or public customer feedback is sparse, it will mean that the process challenges are harder than expected.